Research • Research Areas

The VLSI Group works on designing, verifying, and testing digital VLSI circuits. The Group currently focuses on design and implementation of high performance and low power ASIC and FPGA systems for image/video processing applications.

H.264 Video Encoder ASIC/FPGA Design:

Video compression systems are used in many commercial products such as digital camcorders, cellular phones, and video teleconferencing systems. To improve the performance of existing applications and enable the applicability of video compression to new real-time-applications, a new international standard for video compression has recently been developed with the collaboration of ITU and ISO. The new standard is called by two different names, H.264 and MPEG4 Part 10. H.264 offers significantly better video compression efficiency than the previous standards. The improved efficiency, however, comes with an increase in encoding complexity which makes it an exciting challenge to have a real-time H.264 video encoder implementation.
The VLSI Group is working on designing and implementing a cost-effective (high performance and low cost) and low power H.264 video encoder ASIC/FPGA for real-time portable applications. The Group, so far, designed and implemented a baseline H.264 intra frame coder system that can code 35 CIF frames per second. The hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex II FPGA. The software is implemented in C and runs on an Arm926EJS processor. The system is demonstrated to work on an Arm
Versatile Platform development board. The Group, in addition, designed and implemented an H.264 variableblock size motion estimation hardware that can code 27 VGA frames per second. This hardware is also implemented in Verilog HDL and mapped to a Xilinx Virtex II FPGA.

Faculty: Ilker Hamzaoglu

Recent/Relevant Papers:

-- A high performance hardware architecture for half-pixel accurate h.264 motion estimation, Yalcin, S., Hamzaoglu, i., Proc. 14th Int. Conference on VLSI-SoC, October 2006.

-- An efficient hardware architecture for h.264 adaptive deblocking filter algorithm, Parlak, M., Hamzaoglu, I., Proc 1st NASA/ESA Conference on Adaptive Hardware and Systems June 2006.

-- A high performance and low power hardware architecture for h.264 cavlc algorithm, Fiahin, E., Hamzaoglu, I., Proc. 13th European Signal Processing Conference, September 2005.

-- A high performance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for h.264 video coding, Yalcin, S., Atefl, H. F., Hamzaoglu, I., Proc. 15th Int. Conference on Field Programmable Logic and Applications, August 2005.

Analog and Mixed-Signal Integrated Circuits:

Interfacing transducers to the electronics domain require the proper design of analog amplifiers in association with digital control blocks; hence, a mixed signal integrated circuit results. The tuning of device parameters to meet the characteristics of the particular sensing or driving element requires a thorough assessment of transducer and circuit characteristics.

IC Design for Sensor Interfaces:

The Integrated Circuits Group is heavily involved in research efforts on the design of Application-Specific Integrated Circuits (ASIC) for sensor interfaces. One such example is a circuit used as the drive/receive section of a 2D ultrasonic transducer array. The transducers are fabricated using MEMS technology. The designed integrated circuit incorporates a high-voltage pulse generator section and a low-noise amplifier for the detection of return echoes.
Another example for sensor interface electronics is realized for 4x4 array-based micromachined-chemical
sensor that consist of sensor and built-in heater control / selection circuitry and amplifier. The research in this area is growing with a recently granted research project inquiring readout integrated circuit design for MxN array-based sensors.

Faculty: Yasar Gurbuz, Ayhan Bozkurt

Recent/Relevant Papers:

-- Design of a front-end integrated circuit for 3d acoustic imaging using 2d cmut arrays, Cicek, I., Bozkurt, A., Karaman, M., IEEE Transactions on UFFC, 52(12), 2235-2241, 2005.

-- An interface circuitry for CMOS-compatible, micromachinedchemical sensor arrays, Ayranci, E., Gurbuz, Y., Proc. 206th Meeting of (ECS), Honolulu, Hawaii, USA: October 3-8, 2004.