EE Seminar

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Pushing Back the Many-Core PowerWall

Ulya R. Karpuzcu

Classic CMOS scaling relies on reduction of voltages with lithographic dimensions at every technology generation, which gives rise to a faster speed of operation, a smaller silicon area for the same functionality, and a practically-constant power density. Recent generations have experienced an imbalance in voltage scaling, which has rendered a wildly growing chip power density. While still more transistors can be crammed into the unit chip area at every generation, system cooling constraints prevent the chip power budget from expanding with this growth in power density. As a result, under contemporary scaling, the PowerWall induces a widening gap between the total number of cores that can be integrated on chip and the number of cores that can be powered on – thus, utilized – simultaneously. In this talk, I am going to focus on addressing the Power Wall – a.k.a. dark silicon – problem in two novel and promising ways: By (1) trading-off the processor aging (or wear-out) rate for energy efficiency, and (2) exploring near-threshold voltage operation.

Biography

Ulya R. Karpuzcu has been serving as an assistant professor at the Department of Electrical and Computer Engineering of University of Minnesota, Twin Cities, since Fall 2012. She received the Ph.D. and M.S. degrees in Electrical and Computer Engineering from University of Illinois, Urbana-Champaign. She holds a B.S. in Electronics and Telecommunication Engineering and a B.S. in Computer Engineering, both from ˙Istanbul Teknik Üniversitesi. She is a Fulbright scholar. Her research focuses on the impact of process technology on computer architecture, with the current emphasis being on architectural implications of near-threshold voltage computing and dark silicon.