Master Thesis Defense: Ercan Kalalı
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Low Energy HEVC Video Compression Hardware Designs
 

Ercan Kalalı
Electronics Engineering, M.Sc. Thesis, 2013

Thesis Jury

Assoc. Prof. Dr. İlker Hamzaoğlu (Thesis Supervisor), Assoc. Prof. Dr. Müştak Erhan Yalçın, Asst. Prof. Dr. Hakan Erdoğan 

Date &Time: August, 01st, 2013 – 15:00

Place: FENS  G029

Keywords: HEVC, Intra Prediction, Sub-Pixel Interpolation, IDCT

Abstract

Joint collaborative team on video coding (JCT-VC) recently developed a new international video compression standard called High Efficiency Video Coding (HEVC). HEVC has 37% better compression efficiency than H.264 which is the current state-of-the-art video compression standard. HEVC achieves this video compression efficiency by significantly increasing the computational complexity. Therefore, in this thesis, we propose novel computational complexity and energy reduction techniques for intra prediction and inverse DCT algorithms used in HEVC video encoder and decoder. We quantified the computation reductions achieved by these techniques using HEVC HM reference software encoder. We designed efficient hardware architectures for these video compression algorithms used in HEVC. We also designed a reconfigurable sub-pixel interpolation hardware for both HEVC encoder and decoder. We implemented these hardware architectures in Verilog HDL. We mapped the Verilog RTL codes to a Xilinx Virtex 6 FPGA and estimated their power consumptions on this FPGA using Xilinx XPower Analyzer tool. The proposed techniques significantly reduced the energy consumptions of these FPGA implementations in some cases with no PSNR loss and in some cases with very small PSNR loss.