Faculty of Engineering and Natural Sciences
A10b/240Msps ADC with Double-Sampling Anti-Alias Filter in 90nm CMOS process
Texas Instruments Inc., Dallas-TX
With the HDTV broadcasts becoming widely available and with the requirement
of supporting standard definition TV (SDTV) as well as PC graphics, cost
effective SoC HDTV/SDTV/Graphics solutions are desirable. These SoCs require
analog front end integration on the same die with large amount of digital circuitry. This poses many challenges on the noise performance of the analog circuits especially on the noise performance of the ADCs: 1. DSP requires millions of digital gates which makes digital noise very large. 2. Video processing (for example 3dyc) requires bursts of data transfers between external DDR memory and the SoC. This generates a fixed pattern noise which is more visible on image compared to random noise. 3. Large amount of digital circuit requires smaller geometry processes which may require low supply hence small dynamic range for analog inputs. 4. Couplings increase due to smaller sizes. 5. Different blocks require different clock frequencies. Multiple PLLs may drive different blocks with clock frequencies asynchronous to sampling frequency. Noise coupled to the input by these sources cause rolling type of patterns on image. 6. Video inputs are single-ended. Pipelined ADCs will be briefly introduced, and some design and test techniques will be presented to overcome above issues. Also a 10b/240Msps ADC will be presented using these techniques.
Haydar Bilhan received his BS, and MS degrees in Electrical Engineering from METU, Ankara, Turkey, in 1990 and 1993 and PhD degree in 2000 from Electrical Engineering from Southern Methodist University, Dallas, TX. Since February 1996, he has been with Texas Instruments, Dallas TX, where he focuses on mixed signal and RF CMOS design for video and image processing. He currently holds 13 US patents.
July 30, 2007, 14:40, G032