Scaling the Memory System in the Multi-Core Era of Computing
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Scaling the Memory System in the Multi-Core Era of Computing


The memory system is a fundamental performance and energy bottleneck
in almost all computing systems. Recent trends towards increasingly
more cores on die, consolidation of diverse workloads on a single
chip, and difficulty of DRAM scaling impose new requirements and
exacerbate old demands on the memory system.  In particular, the need
for memory bandwidth and capacity is increasing, applications'
interference in memory system increasingly limits system performance
and makes the system hard to control, memory energy and power are key
design concerns, and DRAM technology consumes significant amount of
energy and does not scale down easily to smaller technology
nodes. Fortunately, some promising solution directions exist.

In this talk, we will examine recent technology, application, and
architecture trends motivating a fundamental rethinking of the memory
hierarchy. Based on this motivation, we will describe requirements
from an ideal memory system suitable for the multi-core era. The talk
will examine questions one would need to answer in approximating the
ideal memory system and possible avenues that seem promising for the
research community to explore. In particular, we will cover our recent
research on tackling challenges related to scaling the capacity,
energy-efficiency, and bandwidth of main memory.  We will examine two
major solution directions: 1) how to design more efficient DRAM
architectures, 2) how to employ emerging non-volatile memory
technologies in main memory, and, if time permits (or, afterwards), 3)
how to enable more predictable and QoS-aware main memory systems.

Onur Mutlu is the Dr. William D. and Nancy W. Strecker Early Career
Professor at Carnegie Mellon University. His broader research
interests are in computer architecture and systems, especially in the
interactions between languages, operating systems, compilers, and
microarchitecture. He enjoys teaching and researching important and
relevant problems in computer architecture, including problems related
to the design of memory systems, multi-core architectures, and
scalable and efficient systems. He obtained his PhD and MS in ECE from
the University of Texas at Austin (2006) and BS degrees in Computer
Engineering and Psychology from the University of Michigan, Ann
Arbor. Prior to Carnegie Mellon, he worked at Microsoft Research
(2006-2009), Intel Corporation, and Advanced Micro Devices. He was a
recent recipient of the IEEE Computer Society Young Computer Architect
Award, CMU College of Engineering George Tallman Ladd Research Award,
Intel Early Career Faculty Honor Award, Microsoft Gold Star Award,
best paper awards at ASPLOS, VTS and ICCD, and a number of "computer
architecture top pick" paper selections by the IEEE Micro
magazine. For more information, please see his webpage at .