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SEMINAR:10 years of making open source RISC-V based computing...

Speaker: Frank Kağan Gürkaynak, ETH Zurich

Title: 10 years of making open source RISC-V based computing architectures

Date/Time: 10 November 2022 / 14:40-15:30 PM

Location: FENS G029

Abstract: In this talk, I will summarize our research around the PULP Platform project (https://pulp-platform.org/) that started almost 10 years ago. We have designed and tested energy efficient computer architectures based on RISC-V cores that have been optimized for use in tiny IoT systems where we embedded them into nano-drones all the way up to large scale computing systems for machine learning acceleration where we have packed 100s of processor cores. All our research and output has been made available using permissive open source licenses and which has allowed our work to be widely used both in Industry and Academia.

Bio: Frank Gürkaynak is the director of Microelectronics Design Center at the Department of Information Technology and Electrical Engineering of ETH Zurich and a senior scientist working with Prof.Luca Benini in the Digital Circuits and Systems Groups of Integrated Systems Laboratory. Their research focuses on energy efficient implementation of digital circuits and systems over a very wide operating range from IoT applications to HPC systems. He obtained his BSc. and M.Sc. degrees from Electrical and Electronical Engineering Department of the Istanbul Technical University and his Ph.D. from the Integrated Systems Laboratory (IIS) of ETH Zurich. He has also been involved in teaching and research at Istanbul Technical University in Turkey, Worcester Polytechnic Institute in U.S.A, EPFL and ETH Zürich in Switzerland.

Current Lectures:

[VLSI 1] [VLSI 2] [VLSI 4] (Accesible only within ETH Zurich domain)

 

Recent Previous Lectures:

P&S offerings of D-ITET: [Essential Skills for your Engineering Career] (Accesible only within ETH Zurich domain)

 

Active Projects :

EU: [Fractal] [Ampere] [EU pilot] [EPI - European Processor Initiative]
[Convolve] [NeuroSoC] 

SNSF: [PEDESITE] [HCSCA] [Tiny Train]

 

Completed Projects:

EU: [Aloha] [Mnemosene] [Oprecomp] [Eurolab4HPC2] [Hercules] [Antarex] [Eurolab4HPC] [P-Socrates] [Galaxy]
SNSF: [Microlearn] [Transient Computing] [Biodev] [IcySoC] [Ultrasound] [YINS] [CMOSAIC] [Qcrypt]
ETH Zurich: [Memristor]

He still actively contributes to research in the following fields:

o   Ultra-low-power processor design:
I am involved in the Parallel Ultra-Low Power (PULP) project.

o   Design and test of digital integrated circuits and system design
Throughout my time at ETH Zürich, I was involved with the test of integrated circuits designed at the Integrated Systems Laboratory, first as an assistant and later as a lecturer for the VLSI 4 course. Together with my group at the Microelectronics Design Center we review all integrated circuit projects and discuss testing strategies.

o   Cryptographic Hardware
I have been involved in evaluating the performance of cryptographic hardware for the past 20 years. Together with semester and master students at ETH Zürich we have implemented a large number of candidate algorithms of AES, SHA-3, e-stream and Ceaser cryptographic algorithm competitions, and have collabrated on many projects that investigates all aspects of side channel security. Recent interests include cryptographic accelerators that are connected to our PULP systems.

o   Open Source Hardware
Our PULP project is one of the more visible open source hardware projects, and I spend some of my time advocating the use of open source hardware in both academia and industry.