Designing the Connected Future _ EE Program Announces a New Course Track: RF Integrated Circuits & Systems

SABANCI UNIVERSITY

Faculty of Engineering and Natural Sciences (FENS)

Electronics Engineering (EE): RF Integrated Circuits & Systems Course Track

Track Mission Statement: To train elite RF and microwave integrated-circuit designers who navigate fluently from solid-state device physics up to complete transceivers and multi-element phased-array systems. This curriculum ensures Sabancı University EE graduates can independently architect, systematically simulate, layout-optimize, and tape-out structural Silicon IP blocks for advanced high-frequency (RF-to-THz) systems within sovereign defense and 6G telecommunication ecosystems.

1. The Curriculum Pathway & Big Picture Outcome

The track is structured as a horizontal four-phase progression, moving logically from solid-state foundations to industrial-scale high-frequency system deployment. The unified learning outcome bridges silicon micro-engineering with free-space wireless and aerospace applications in a single, structured pipeline.

Phase 1 — Junior Fall: Foundation

EE 307 (Semiconductor Devices):  The Physics Bedrock

Establishes the solid-state device physics and carrier mechanics behind every integrated circuit: pn junctions, BJT/FET operation, energy-band diagrams, and the derivation of the I-V relationships used throughout the rest of the track.

EE 303 (Analog Integrated Circuits):  From Devices to Analog Cells

Translates device physics into functional multi-transistor analog cells — current mirrors, differential pairs, cascodes, and multi-stage amplifiers — designed, simulated, and laid out in the industry-standard Cadence environment with full attention to noise, stability, PSRR/CMRR, and power.

 

Phase 2 — Junior Spring: The High-Frequency Bridge

EE 306 (Introduction to RF & Microwaves):  Where Circuits Meet Waves

The critical bridge linking lumped analog circuits to distributed microwave networks. Students master transmission-line analysis, the Smith Chart, S-parameters, and impedance matching, then design and physically measure high-frequency amplifiers using Keysight ADS and vector network analyzers. 

 

 

EE 302 (Digital Integrated Circuits): runs alongside to complete the mixed-signal foundation: large scale integrated (LSI) circuits; inverter circuits, static and transient operation; CMOS logic implementation, full-custom gate design, mask layout fundamentals; static and dynamic logic circuits; sequential logic circuit designs; non-volatile semiconductor memory structures; static and dynamic random access memory design.

Phase 3 — Senior Year: The RFIC Core

EE 411 (RFIC I_updated content):  The Crown Jewel, Part I — Front-End Design & Layout

Precise schematic design and layout execution of RF front-end blocks in CMOS and SiGe BiCMOS: low-noise amplifiers, switches, attenuators, phase shifters, and true-time-delay circuits — evaluated through gain, noise figure, isolation, linearity, and stability, and carried through a full spec-to-report RFIC design flow with electromagnetic verification.

EE 412 (RFIC II)*:  The Crown Jewel, Part II — Non-Linear Blocks & Full Transceivers

Expands capability into power amplifiers, mixers, VCOs, and PLLs, and elevates the perspective to complete transceiver architectures (heterodyne, homodyne, low-IF, direct conversion). Students translate communication, radar, and phased-array system requirements into circuit-level specifications and execute a complete design flow from specs through layout, EM verification, and documentation.

EE 420 (Phased Arrays for RADAR & Wireless Communications)*:  The System Apex

Scales single-chip skills into multi-element systems: array factors and beamforming architectures, adaptive processing (STAP, DoA estimation), cascade noise-figure and link budgets (G/T, EIRP, radar equation), and radar/communication waveform design — synthesized into an end-to-end phased-array system evaluated in MATLAB.

EE 234 (Vertical Integration & Professional Seminar)*:  The Career Accelerator

The track’s organic mentorship hub tying undeclared-EE students, sophomores, juniors, and seniors together weekly with industry stakeholders: elective-pool mapping for sophomores, internship-targeted portfolio building for juniors, and sponsor-defined ENS 491/492 proposal development for seniors.

Supporting Electives:  Depth on Demand

• Senior Fall (Phase 4.1): 

  EE 409 (Microwaves) 

  EE 407 (IC Fabrication) 

  EE 404 (MEMS) 

  — high-frequency propagation and physical fabrication foundations alongside RFIC I.

   

• Senior Spring (Phase 4.2): 

  EE 440 (Mixed-Signal ICs) 

  EE 406 (Antennas) 

  — advanced specialization in data converters, frequency synthesis, antenna, and sensor integration.

Direct Pipeline Notice: This senior core directly prepares you for and feeds straight into your ENS 491 / ENS 492 Graduation Projects — sponsor-defined Silicon IP designs executed under realistic MPW tape-out constraints with ADI, Axiro, IHP, KIT, and VTT.

2. Important Curriculum Notice: New Course Proposals

Three components of the senior core are new course proposals currently moving through the approval pipeline (marked with * throughout this document):

• EE 412 (RFIC II): completes the two-semester RFIC crown-jewel sequence with PA, mixer, oscillator/PLL, and full-transceiver design.
• EE 420 (Phased Arrays): delivers the system-apex capability for radar and wireless communication applications.
• EE 234 (Vertical Integration & Professional Seminar): establishes the weekly all-ranks mentorship and industry engagement platform.

* Note: These are new / proposed courses and students intending to follow this track are strongly encouraged to complete EE 307, EE 303, EE 302 and EE 306 in their junior year, as these provide the critical device and high-frequency background required for the 400-level RFIC sequence.

3. Industry & Research Partnership Matrix

The track thrives through active, structural partnerships with national and international microelectronics leaders, creating direct pipelines for research, internships, and careers:

• IHP Microelectronics (Joint Virtual Lab & Foundry): direct access to advanced 0.13µm SiGe-BiCMOS PDKs, summer internships, and joint theses with real tape-out experience.
• Analog Devices (ADI): mentorship and placement paths through its Istanbul Design Center.
• Axiro Semiconductor: sponsors graduation capstone projects on advanced Satcom and 5G/6G front-end hardware.
• Karlsruhe Institute of Technology (KIT) & VTT: collaborative sub-THz research and joint MSc/PhD candidacy paths for top-tier graduates.
• EDA & Lab Infrastructure: premium licenses (Cadence Spectre, ADS, Momentum, SONNET, Ansys) and state-of-the-art test instrumentation co-sponsored by industrial system houses.

4. Faculty & Advising Contacts

For enrollment advising, comprehensive curriculum planning, or graduation project alignment, please reach out to the faculty representatives heading this track:

• Melik Yazıcı (Faculty Representative)
• Yaşar Gürbüz (Faculty Representative)