Seminar: Prof.Gain Kim
Time: January 4, 2023 @13:40
Place: FENS G035 (Physical only)
Please find the abstract of the talk and the short bio of the speaker below:
Abstract: Ever-increasing demands for higher I/O bandwidth in network infrastructures and data centers have been motivating the high-speed SerDes to increase its per-lane data rate by a factor of two every four years. With the increasing data rate to 112Gb/s per lane, PAM-4 with ADC-DSP-based RX has become the most commonly employed modulation and RX architecture for ultra-high-speed SerDes. Network switch SoCs now support 51.2Tb/s with 100Gb/s PAM-4 SerDes, maintaining the same pin counts.Moreover, the recent emergence of chiplet in high-performance processors created new SerDes applications, especially with excellent energy efficiency and lane density.However, while the SerDes data rate keeps increasing over the years, the energy efficiency of the link does not improve at the same rate. This talk overviews recent advances of SerDes in various applications, underlying challenges and introduces emerging SerDes architectures beyond PAM-4.
Bio: Gain Kim received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the Ecole Polytechnique Federal de Lausanne (EPFL), Lausanne, Switzerland in 2013, 2015, and 2018 respectively. From 2016 to 2018, he was with IBM Research Zurich, working on ADC-based wireline receiver designs. From 2018 to 2020, he was with KAIST as a postdoctoral fellow, and from Nov. 2020 to Jan. 2022 he was with Samsung Research, Seoul, South Korea, as a staff engineer working on a baseband modem for 6G wireless communications. In Jan. 2022, he joined Daegu Gyeongbuk Institute of Science & Technology (DGIST), Daegu, South Korea, where he is currently an assistant professor. His current research interests include the design of high-speed ADC, ultra-high-speed SerDes design, modulation techniques for ADC-based serial links, as well as multi-chip computing systems with energy-efficient interfaces.